Generally, electrical and burn-in testing is frequently carried out on diced packaged or unpackaged semiconductor chips. Tustaniwskyj, et al., U.S. Pat. Nos. 5,821,505 and 5,844,208 describe a procedure to estimate the temperature of diced semiconductor chips based on the measured temperatures of a heat sink and an electric heater interposed between the chip and the heat sink. The estimated temperature is then used to control the heater power and temperature to maintain the chip at a desired temperature during testing.
As semiconductor devices get smaller and the pressure to cut semiconductor processing and testing costs and time has grown, two trends have emerged. The first trend is the increased power dissipation, and hence self-heating of semiconductor devices. A second trend is a drive toward performing device burn-in and electrical testing at the wafer level before the wafer is cut into individual device chips to decrease testing time and cost. However, prior thermal control systems generally do not provide a sufficient amount of temperature control for wafers and high power dissipation chips undergoing electrical and burn-in testing.